The present invention relates to a circuit for correcting a duty cycle of a clock signal, and more particularly, to duty cycle correction circuits which may be used when a delay line is coarse compared to a conventional duty cycle correction circuits.
Duty cycle correctors are used to provide accurate clock signals in systems such as semiconductor memory devices. In particular, when a duty cycle of a clock signal is substantially offset from a value of 50% in a semiconductor memory device using a double data rate (DDR) interface, the width of a data section output at a rising edge of the clock signal is different from that of a data section output at a falling edge of the clock signal. Thus, the role of the duty cycle corrector is important.